A Full-Digital Synthesizable Tdc Asic Design

In this study, a full-digital synthesizable time-to-digital converter (TDC) is proposed to apply to the time-based position emission tomography (PET). Generally, FPGA is a platform to implement TDC in synthesizable design flow. However, in application-specific integrated circuit (ASIC) design flow, the TDCs are only implemented in full-custom design flow, which employs human to layout the TDC circuits. Thus, a systematic design flow by synthesizing from standard cell library is proposed in this work. Based on this design flow, the design time can be saved, and the uncertainty in manual layout can be also avoided.This work employs histogram method to calibrate the non-linear effect in the ASIC TDC design. The proposed self-calibration method can improve the differential nonlinearity (DNL) values hugely. Therefore, the proposed ASIC TDCs can robustly cope with the temperature and voltage effect. To conclude, this work proposes a synthesizable design flow for ASIC TDCs, and aims to cope with the high time-resolution as much as possible in PET system.

Project ID:PB10708-2181
External Project ID:MOST107-2221-E182-066