A Study on the Adaptive Negative Capacitance for High Psrr and Fast Transient Low-Dropout Regulator

Project: National Science and Technology CouncilNational Science and Technology Council Academic Grants

Project Details

Abstract

One of the most critical attributes of low dropout regulators (LDOs) in increasingly complex systems on chip (Soc) is high-power supply rejection ratio (PSRR), this project presents a feed-forward path from the (LDO)’s supply input to the output, capacitor-less low dropout regulator (CL-LDO) with capacitance multiplier and adaptive negative capacitance for noise cancellation to increase power supply rejection (PSR) and fast settling time (Ts). The CL-LDO achieves a −80 dB low frequency at 10 KHz for 500 mA of load current (IL ). The CL-LDO achieves load current switching from 10nA to 500mA for 1us, 100 ns of edge time. The CL-LDO was fabricated in CMOS 180nmtechnology, consumes IQ of 12.5μA, has a dropout voltage of 25 mV for IL of 500 mA.

Project IDs

Project ID:PB10907-4050
External Project ID:MOST109-2221-E182-053
StatusFinished
Effective start/end date01/08/2031/07/21

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