Adaptive Ipc Vliw Processor and Energy-Aware Compiler (2)

In the deep submicron era, static power plays the major role in the total power consumption of a chip. To the change on power consumption profile, adaptive IPC (instructions per cycle) processors were proposed to save static energy for program execution. This project is to study the architecture and compiler design for AIPC (adaptive IPC) processors. Based on the emerging multi-voltage technologies for VLSI design, we propose an AIPC-VLIW processor architecture featuring distributed register files with multiple power domains. The architecture is designed to make power consumption scales with IPC and left the energy optimization task to the compiler. The objective of the energy-aware compiler is to minimize total energy consumption subject to given performance requirements. Issues for the compiler design include (1) operation mapping and resource allocation for software pipelining on a kernel loop (2) fixed makespan instruction scheduling to minimize static energy for given performance requirement (3) replicated register allocation on distributed register file to reduce data transfer energy (4) global register allocation for a multi-voltage register file to reduce power consumption on register files. With this project, we setup the theoretical foundation on power domain partitioning and resource allocation for AIPC processors. These results will be the foundation on advanced AIPC technologies, such as AIPC superscalar processors and global compiler optimization.

Project ID:PB10007-7248
External Project ID:NSC100-2221-E182-031-MY2