Algorithmic Noise-Tolerant Multiplier Architecture Design

With the progress of VLSI process technology, the design complexity and the transistor density in SoC systems increase rapidly, which leads to the power consumption and power density in the SoC designs also increasing rapidly. Low power design becomes the major design challenge in the SoC designs. However, one of the major challenges in ultra-low power and nano-scale circuit design is noise fluctuation. As CMOS designs are keeping miniaturized down to the nano-scale CMOS designs, how to enhance the noise-immunity of VLSI circuits and make them operate correctly under low supply voltage is a very important research topic. In this project, we will develop some algorithmic noise-tolerant techniques to enhance noise-immunity in VLSI digital circuits. We will implement the 32-bit low-voltage noise-tolerant multiplier chip through UMC 90nm process. The noise-tolerant multiplier is expected to operate under the 0.45V, with 10-8 BER. The architecture of noise-tolerant multiplier is based on algorithmic noise-tolerant architecture. We focus on developing the main block circuit and predictor circuit design in this project. To achieve low-voltage operation, the main block multiplier must operate in high speed and the predictor must contain high-precision characteristics. Therefore, we will design a high-speed multiplier and a high-precision fixed-width multiplier in this project. They are two major design goals in this project.

Project ID:PB9803-0136
External Project ID:NSC98-2218-E182-003