Charge Pump Match Techniques for Dll/Pll

Phase-locked loop (PLL) and delay-locked loop (DLL) are widely used as a clock generator in microprocessors, memory, and communications integrated circuit in 3C products. In the past years, the more researches focus on the fast-locked and high-frequency output techniques. During recent years, the fast-locked technique and high frequency input techniques become more matured than before. The researchers try to study the signal quality now. They are focus on how to improve signal quality nowadays. The charge pump is design to change the voltage level in the PLL and DLL by charging and discharging the loop filter. However, the charge pump has current mismatch problem. The distortion of the charge pump is due to the unmatched MOS transistor characteristics and process-voltage-temperature (PVT) variation. This problem cause a static phase error between reference signal and output signal after the PLL and DLL are locked. Therefore, in our research, we focus on the current mismatch to improve signal quality and synchronization The purpose of this project is divided into two years. The first year will design a fast-locked and phase error calibration circuit for DLL by using hold-time of D-type Flip-flop (DFF). The second year will design a spur reduction and phase error calibration in PLL with setup-time of DFF.

Project ID:PB10108-2808
External Project ID:NSC101-2221-E182-077