Compiler-Directed Power Management for Innovative Memory System

This project is to design energy-efficient memory system aimed at providing high capacity storage with limited energy cost. The basic idea is to deploy power-gating on RAM and the RAM is backed up with a large pool of non-volatile memory for retention. The key issue is to develop compiler optimization algorithms to insert power-gating instructions to control the active size of the RAM. Originally planned as a 3-year project, the research issues are (1) Develop compiler algorithms for program partitioning, (2) Devise analytical model to derive optimal RAM buffer size for energy efficiency, and (3) Develop energy simulation model of hybrid memory system. At the end of the first year, we successfully developed loop-based program partitioning algorithm for the optimizing compiler. Based on profiling information, the algorithm partitions the application program to balance between improving resource utilization and power-gating overhead. Evaluation shows significant energy saving achieved by the compiler optimization. The result has been accepted to be published on IEEE Transactions on VLSI Systems. With the success of the algorithm, a general framework for quantitative management on power-gated hardware resource is established. The results serve as the foundation for power-gated memory systems research for further study.

Project ID:PB10408-5747
External Project ID:MOST104-2221-E182-002