Cost-Efficient Noise-Tolerant CMOS Digital Circuits Design (II)

With the progress of VLSI process technology, the design complexity and the transistor density in SoC systems increase rapidly, which leads to the power consumption and power density in the SoC designs also increasing rapidly. Low power design becomes the major design challenge in the SoC designs. However, one of the major challenges in ultra-low power and nano-scale circuit design is noise fluctuation. As CMOS designs are keeping miniaturized down to the nano-scale CMOS designs, how to enhance the noise-immunity of VLSI circuits and make them operate correctly under low supply voltage is a very important research topic. In this project, we will develop some noise-tolerant techniques to enhance noise-immunity in VLSI digital circuits. We will implement the 32-bit noise-tolerant ALU chip through TSMC 90nm process. The noise-tolerant ALU is expected to operate under the 0.2V, with 10-8 BER. In static CMOS circuits, our designs are based on H-tree MRF theory to simplify the MRF mapping in transistor level. To merge the valid minterm generator and valid minterm feedback loop, we can develop the cost-efficient noise-tolerant MRF VLSI circuits, which not only consume lower power, operate faster, but also perform higher noise-immunity. Through dividing the whole MRF network into many small-scale MRF sub-networks and optimizing them through cross-region MRF network combination, we expect that we can reduce overall hardware complexity and still achieve high noise-tolerance. In dynamic CMOS circuits, we will design the cost-efficient dynamic CMOS circuits in this project. Through TSPC-based noise isolation mechanism, we will develop the contention relaxed noise-tolerant technique through noise path isolation. By this way, we can enhance the noise tolerance of dynamic circuits more effectively. Moreover, the performance overhead for enhancing the noise-tolerance can be greatly reduced, especially the overhead in computation delay. As comparing with the noise-tolerant techniques by “avoiding dynamic floating nodes”, we can perform higher noise-immunity. As comparing with the noise-tolerant techniques by “raising the source voltage”, we can spend lower performance overhead. Instead of enlarging the noise-tolerant transistor size, our method is to enhance the noise-immunity by isolating the noise propagation path. Therefore, we can further improve the noise-tolerance of dynamic circuits and bring dynamic circuits to operate under low SNR environments. Moreover, the performance overhead for enhancing the noise-tolerance can also be greatly reduced.

Project ID:PB9907-4029
External Project ID:NSC99-2221-E182-063