Crosstalk Constrained Optimal Layout Design for High Speed and High Desity VLSI Circuits

  • Lee, J. Yen (PI)

Project: National Science and Technology CouncilNational Science and Technology Council Academic Grants

Project Details

Project IDs

Project ID:PB9009-0967
External Project ID:NSC90-2215-E182-002
Effective start/end date01/08/0131/07/02


  • Integrated circuit design
  • VLSI
  • Crosstalk noise
  • Optimal design


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