Project Details
Abstract
The purpose of the DDR3 is developed for the computing and graphic application, such as high-speed desktop server and workstation. Those applications need to process large amount of the data to make the images running smoothly in the computer screen. The data rate of DDR3 memory system has reached 1600MB, with low power consumption. The system is applied a reference clock for the DDR3 system for input. Therefore, the data rate is increased due to the system is used the reference clock to synchronized with. The market is respect DDR3 system to be increased. To respond to this market demand with as much flexibility as possible, we have developed a delay-locked loop (DLL) for the DDR3 system.
DLL have been widely used for the designing high-speed memory interface circuit or clock de-skew, and multi-phase clock generation. In those applications, the DLL offers a better jitter performance than the phase-locked loop (PLL), due to the reference clock jitter and noise generated by power supply and subtracted noise disappear at the end of the delay line. The DLL is good alternative for PLL in those applications and has a good phase tracking ability.
This DLL is composed with voltage controlled delay line (VCDL), charge pump (CP), phase detector (PD), and all-digital calibration circuit. This system operates with VCDL in 400MHz ~ 800MHz. The system is offered a low phase error jitter and a charge pump calibration.
This project will be developed a DLL for DDR3 system.
Project IDs
Project ID:PB9706-1898
External Project ID:NSC97-2218-E182-001
External Project ID:NSC97-2218-E182-001
Status | Finished |
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Effective start/end date | 01/01/08 → 31/10/08 |
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