Delay-Locked Loops with Phase Error Calibration

In recent years, due to the popularity of high-frequency circuits, made to improve the method of phase-locked loop is no longer confined to the past. Synchronous communication system uses a clock signal as a timing reference, this reference signal in accordance with the known relationship between the transmit and receive data; the difficulty lies in maintaining this relationship processes, voltage and temperature changes will change the clock signal and data signal timing relationships between the. The problem with the signal transmission rate increases has become more important, this has restricted the system transmits data at high rates of capacity. Delay-locked loop is widely used in solving the time of the phase error and clock jitter problems. Relative to the phase-locked loops, delay locked loop has the advantage of unconditional stability. Moreover, because of the delay phase-locked loop using a voltage control delay line does not accumulate noise. Therefore, the delay -locked loop also provides better jitter output, while in dealing with synchronization issues, the delay-locked loop is the better choice. The study of this project is that, because of the charge pump of the current mismatch caused by the phase error. How to solve the delay -locked loop phase correction of the error correction, and to digitally will not be affected by many factors, the advantages of quickly changing the function of the way to render the circuit. To enhance the interface circuit performance and applications is what our objective of the study.

Project ID:PB9907-12673
External Project ID:NSC99-2221-E182-064