Project Details
Abstract
Since Moore’s Law will reach to the physical limit in the near future, the diversification (or heterogeneous chip integration) has gained more attention recently, due to its cost effectiveness, feasibility, and compatibility to current manufacturing infrastructures. To realize this diversification, a through-silicon-via (TSV) interconnect technology plays an important role of integrating multi-chips together in three-dimensional (3-D) manners as a system or sub-system. However, the TSV technology implemented in the 3-D IC integration is facing shortcomings such as process complexity, relatively high cost, low yield rate and thus low market demand. As a result, alternatively semiconductor companies started developing 2.5D IC integration technology as a transition approach, which applies a TSV silicon interposer as a platform to interconnect and integrate heterogeneous chips horizontally and vertically. The main goal of this project is two-fold: 1) the first year to investigate the effect of material properties, geometry and process parameters on thermal deformations (warpage) and stresses of the TSV silicon interposers during the manufacturing process; and 2) further to determine the strength and thermal reliability of this interposer in the second year. The methodologies used includes experimental methods (Twyman-Green interferometry, shadow moiré, various strength test methods, acoustic emission and so on), a finite element numerical method and related theories (Stoney equation, Timoshenko bi-material and Suhir theory). The test samples and process conditions will be supported by local semiconductor foundries and packaging houses. The project will eventually create a close collaboration with local semiconductor companies and packaging houses and further help them tackle this hot issue which the world-wide semiconductor companies and academia are currently facing. It is hopeful that this search collaboration will show a good example and success of a partnership between academia and industry.
Project IDs
Project ID:PB10501-3727
External Project ID:MOST104-2221-E182-001-MY2
External Project ID:MOST104-2221-E182-001-MY2
Status | Finished |
---|---|
Effective start/end date | 01/08/16 → 31/07/17 |
Keywords
- TSV technology
- 3-D IC integration
- 2
- 5D IC
- Si Interposer
- Warpage
- Reliability
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