Design and Optimization for Hybrid Memory and Process Scheduling

NVM (Non-Volatile Memory) has been introduced in different forms in the past decades to be memory, storage or some other devices. The storage-class memory concept is also proposed to use byte-addressable NVM for both main memory and storage at the same time, and for real products, Intel also plans to release its byte-addressable NVM device in the open market in 2018. However, most of the existing designs of operating system routines and data structures are developed for the architecture having DRAM as main memory and using block devices as storage. For the current study results of NVM, as shown in the related work section of this proposal, NVM is usually used as some additional device to main memory or to storage. The goal of this project is to jointly consider the memory-storage management on NVM and the task scheduling with DVFS/DPM (Dynamic Voltage and Frequency Scaling/Dynamic Power Management) supports to optimize the runtime performance, reduce binary and data loading latency, and/or reduce the total energy consumption of a system. In order to achieve the goal of this project, we have to understand the hardware characteristics and profile the performance of computing and memory devices in the first year. The profiling results should be collected and modeled in a simulation platform. With the simulation platform, we can study and analyze different combinations of SRAM, DRAM, NVM, and NAND flash, and suitable applications for each evaluated memory-storage combination should be tested and identified. Furthermore, the computing time of tasks should be then included into the simulation platform to understand the overall system performance. In the second year, we are going to improve data structures and operating system routines to better fit the characteristics of NVM. NVM usually consumes more energy and latency on write operations (compared with read operations). Thus, reducing the number of writes of a data structure can not only improve the performance of using the data structure but also reduce the energy consumption. This direction can be further extended to reduce the number of bit flips of all writes. Another important issue is that the number of write cycles of NVM is limited. To address the endurance problem of NVM, our new data structures have to evenly distribute write operations to all bytes or pages of a NVM device. In the third year, based on the implemented simulation platform in the first year and the developed data structures and system routines in the seconded year, we will further leverage DVFS and DPM techniques to reduce the energy consumption of a system with the joint consideration of task scheduling and NVM management for both main memory and storage. Finally, the research and implementation results should be demonstrated with target applications on Intel 3D XPoint memory and Xilinx Zynq UltraScale+ ZCU10 platforms with the support from the main project.

Project ID:PB10901-3470
External Project ID:MOST107-2221-E182-012-MY3