Developments of Fundamental Theories and Experimental Methods for Characterizing Ic Package Warpage and Die Strength in Heterogeneous Integration Applications

In an application of heterogeneous integration packages such as advanced 2.5D and 3D IC packages, the controls of thermal warpage and internal stresses in the packages and the strength characterization of its inside thin silicon TSV chips are very important during the stacking process and subsequent reliability testing. Studies related to theoretical analysis of thermal warping behavior in such packages and the evaluation of the bending strength of thin silicon chips with TSVs are also lacking in the literature. This study is going to provide a theoretical solution and experimental measurement of strain-gage method to the thermal deformation of heterogeneous integration packages during solder reflow, to develop novel methods for characterizing bending strength of thin silicon TSV chips, and to provide detailed investigation on the effects of some parameters on thermal deformations (warpage) and stresses of heterogeneous integration packages during the manufacturing process and subsequent reliability testing. This project has three phases: (1) in the first year to modify and extend the Suhir theory to calculate thermal deformations of the 2.5D IC package, and then to validate those by experimental and finite element results, in addition to propose the new measurement of thermal deformation by a strain gage method; (2) in the second year to newly develop bending strength test methods for thin silicon chips by considering their large deformation (geometrical nonlinearity) and associating with acoustic emission method during the tests, and further to apply those methods to evaluate the thin silicon TSV chips which are often seen in 2.5D and 3D IC packages; and (3) in the last year, based on the previous two-year research results, further to evaluate the effects of material properties (including residual stresses of molding compound materials), geometry and process parameters on thermal deformations (warpage) and stresses of heterogeneous integration packages during the manufacturing process and subsequent reliability testing. The methodologies used in this study includes experimental methods (Twyman-Green interferometry, shadow moiré, strain gage, acoustic emission method, 3-point bending, and PoEF), a finite element numerical method and related theories (Timoshenko bi-material and Suhir theories). The test samples and process conditions will be supported by local semiconductor foundries and packaging houses. The project will be closely cooperated with local semiconductor packaging houses to further help them tackle those hot issues which the world-wide semiconductor companies are currently facing.

Project ID:PB10901-3451
External Project ID:MOST108-2221-E182-045-MY3