Domain Specific Language and Compiler for Energy Efficiency on Data-Intensive Applications

  • Ma, Yung-Cheng (PI)

Project: National Science and Technology CouncilNational Science and Technology Council Academic Grants

Project Details


The coming of dark silicon age requires technologies for effective power management and rapid development of application-specific accelerators. On the other hand, various data-intensive applications emerged in recent years and these applications require strong computing power as well as good energy efficiency. This project is aimed to develop technologies for rapid development of energy-efficient accelerators targeting data-intensive applications. We propose a memory-rich architecture, featuring power-gated scratch-pad memory (PG-SPM), with drowsy mode control through extended Halide language and compiler. The Halide language will be extended with directives to generate nested loops with operation scheduling and custom hardware synthesis for data-intensive applications. The key technology, named parallelism scaling with data layout (PSDL), will be developed to transform the Halide generated loops with energy-efficiency optimization on both computational units and the memory hierarchy. Research issues include (1) stencil algebra to describe the scheduling and data layout for data-intensive computing, (2) the virtual pipeline slicing and replication algorithm for software pipelined schedule and custom hardware synthesis, and (3) the data layout algorithm which consists of two-dimensional layout condense. Through the two-year project, we expect to develop hardware and software platform for energy-efficiency optimization over data-intensive applications.

Project IDs

Project ID:PB10907-3529
External Project ID:MOST109-2221-E182-037-MY2
Effective start/end date01/08/2031/07/21


  • Halide language
  • energy efficiency
  • power gating
  • domain specific architecture


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