High Uniformity P-Gan Gate Power Device on 6-Inch Soi Substrate and Its Package Technology( I )

In order to promote the development of industrial environment in Taiwan in 2016,we will actively promote the “Green” industrial policy. The government proposedthe future plan in 2025 to reach the goal of non - nuclear homes and this goalmust be to promote the green energy to replace the current nuclear powersupply. Past 5 years, 6-inch GaN related field-effect transistor technologyexhibited a great success and huge progress such as material epitaxy, devicefabrication, and package method in the worldwide. In addition, due to the matureGaN FET technology, the fabrication cost was also reduced. GaN material hasattracted so much attention due to their several special properties: fine thermalstability, high breakdown voltage, high electron velocity, and high current density,and so on. GaN could be applied for high frequency and high voltage operation athigh temperature environment, especially such as future switching power supplyapplication. In this four year project, we will propose a new GaN normally-offHEMT with high uniformity and reproducibility on 6-inch SOI substrate for DC/DCand AC/DC power switching device for next generation power saving concept.The first year a high device uniformity p-AlGaN gate normally-off power devicewill be proposed base on AlN etching stop layer design and this compositedSchottky barrier layer design can overcome the p-AlGaN over etching problem.Moreover, the microwave annealing technique will also be adopted for this thincomposited barrier layer and the Mg out diffusion can also be minimized for p-AlGaN gate. For integration consideration, GaN diode on HEMT wafer is alsoimportant. Therefore, a zero turn-on voltage GaN diode will be proposed anddemonstrated on the same wafer together with high breakdown voltage. To　further improve the thermal dissipation during device operation, we will depositthe diamond-like carbon on gate terminal. For system level, reduce device COSSand CISS are two main methods and the novel SOI substrate will be adopted tofurther suppress substrate induced parasitic effect. For last year of this four yearproject, we will try to integrate the gate drive IC and power device with 3D AlNpackage for high-level power IC integration and the IC is expected to be qualifiedby high temperature and high humidity industrial evaluations.

Project ID:PB10907-5218
External Project ID:MOST109-2218-E182-001