Improvement of Resistive Memory Switching Performance by Using Novel Interfacial Layer Approach

According to the Industrial Technology for Semiconductor (ITRS) requirements, the nanoscale (＜100 nm) nonvolatile memory devices with low voltage (＜3V) and low current (~1 mA), high-speed writing (＜50 ns) and erasing (＜50 ns) of data, highly non-volatility (＞10 years of retention), high endurance (＞108 cycles) with multi-level application, highly reproducible and uniform, and highly compatible with CMOS technology are very important candidate for the next generation of mass production. In our daily life, the portable memory devices such as digital camera, video camera, mobile phones, personal digital assistance (PDA), iPOD, portable high quality notebooks, high-speed computers and DVDs so on are always using. Low power operated electronic goods with high speed and huge non-volatile memories are always demanded by customers. It is well known that the floating gate nonvolatile memory devices are using in those portable electronic goods in a 45 nm technology node recently. According to Intel’s announcement, the floating gate memory devices can be scaling down to 32 nm technology node. According to the Macronix, the poly-Si-oxide-[silicon-nitride (Si3N4)]-oxide-Si (SONOS) charge trapping memory devices is difficult to scale below 45 nm technology node. One of the possible solutions to scaling the non-volatile memory device by using resistive switching memory is studying by Macronix, Taiwan; Samsung, South Korea, Qimonda, Germany; Spansion, USA; Sharp, Japan; NEC Corpotaion, Japan; Sony, Japan, and etc. Due to the unknown mechanism of resistive switching memory and issues of processes, it is not an easy task to control the stable switching. To overcome those problems, we propose the new concept of resistive memory device using interfacial metal layer which can not only improve the adhesion between the electrode and solid electrolyte but also can improve the resistive performances such as uniformity, stable resistance states, strong Cu chain formation in the electrolyte, etc. In this work, we will focus on the high-k Ta2O5 or Gd2O3 films or solid electrolyte and novel Ti or Sm interfacial layer. In this study, a single oxygen vacancy chain or Cu metal chain can be formed through the interfacial layer. A new scheme of nonvolatile memory devices with interfacial layer of Ti or Sm for Cu chain formation in the high-k films will be designed and fabricated for the next generation of mass production. The resistive memory devices can be operated with extremely low voltage and current, high-speed of data writing and erasing, and highly non-volatility and uniformity. Our interfacial layer approaches to realize and product using those new concepts of memory devices have been discussed point-wise below. Part 1: High-k Ta2O5 or Gd2O3 resistive switching memory devices using Ti or Sm metal interfacial layer approach 1. Design and investigation of high-k Ta2O5 or Gd2O3 resistive switching memory using IrOx or Pt metal electrode for small via of ~0.2 mm. The high-k film can be deposited by sputtering or E-gun system. 2. Evaluation of resistive switching memory characteristics such as current-voltage, endurance, retention, etc. 3. Tuning the thickness of high-k films to find the resistive switching mechanism. 4. Design and fabrication of novel resistive switching memory using a IrOx/Ti (or Sm)/Ta2O5 (or Gd2O3)/W (or TiN) structure. 5. Tuning the thickness of Ti or Sm metal for better performance, i.e., strong single chain of oxygen vacancy or oxygen rich. 6. Investigation of thermal stability of the novel resistive memory devices. 7. Resistive memory device fabrication with small via of ＜100 nm. 8. Optimization of memory structure, measurement and understanding the nanoscale (22 nm) resistive switching memory. 9. Realization and clear understanding the resistive switching mechanism. 10. Controlling a single chain formation through the novel interfacial layer of Ti or Sm metal oxide. 11. Integration the resistive element with a series transistor. 12. Evaluation of that memory circuit and evaluation of multi-level operation. 13. Design and fabrication of 1 kb memory circuit with joining company. 14. It can be used for very low voltage and low current operation and super fast nanoscale non-volatile memory devices. 15. It can be used for below 22 nm technology node. Part 2: Single Cu chain formation in the high-k Ta2O5 or Gd2O3 solid electrolytes by using novel interfacial layer of Ti or Sm metal 1. Design and fabrication of Cu chain in a high-k Ta2O5 or Gd2O3 solid electrolyte using a small via of 0.2 mm. 2. Evaluation of memory switching characteristics such as current-voltage hysteresis, endurance, retention, etc. 3. Evaluation of thermal stability of the Al./Cu/Ta2O5 (or Gd2O3)/W or TiN structures. 4. Novel conductive bridging memory devices using Ti or Sm interfacial layer in an Al/Cu/Ti (or Sm)/Ta2O5 (or Gd2O3)/W structure. 5. Evaluation of memory switching characteristics. 6. Tuning the thickness of Ti or Sm interfacial layer. 7. Realization of good memory devices with different annealing temperatures. 8. Investigation of stable switching characteristics. 9. Thorough investigation of novel high-k solid electrolytes with small via of ＜100 nm. 10. Investigation of a single Cu chain formation in the Ti or Sm interfacial layer. 11. Measurement and understanding of nanoscale memory characteristics (~22 nm) for novel interfacial layer approach. 12. Design and fabrication of 1kb memory array circuits with 13. Realization of memory circuits for production and joining with local company, Taiwan R.O.C. 14. The resistive memory circuit could be realized with extremely low voltage as well as current, highly nonvolatile for below 22 nm technology node. 15. It can be used for multi-level applications. 16. It is believed that generous effort of our nonvolatile group will bring very good outcomes which can be useful for new generation of mass production. 17. It is very interesting and challenging task to control the stable switching through the

Project ID:PB9808-2406
External Project ID:NSC98-2221-E182-052-MY3