Integrated Design and Testing for a Physiological Examination SoC(III)

The whole program project is aimed at designing a SoC (System-on-Chip) for physiological examination. The target SoC is an embedded system using the ARM922T as its core processor. This project (subproject 4) will deal with the integrated design of the hardware components and the development of the associated firmware. In addition, we will study about testing and DFT (design for testability) for SoC. The goals of this project include: 1. Integrated design of the circuit units in the physiological examination SoC We will deal with the integrated design of the SoC circuit units, including the AHB to APB bridge, the GPIO (General Purpose Input Output) interface unit, the LCD controller, UART, the baseband interface unit, the interrupt controller, the timer unit, and the memory controller. Each test pattern is considered being transferred via AMBA bus to embedded circuits. It includes transformation of the test patterns to the forms required for testing the embedded circuits designed for testability. 2. Design of the system architecture and implementation of the firmware We will deal with the design of the system architecture, such as the planning of memory map, I/O units, and the interrupt vector table. Also, we will implement the firmware for the SoC system, such as the interrupt service routines, and BIOS. 3. Testing and design for testability for SoC The testing and DFT part of this project is going to design the boundary circuit suggested by P1500 as follows: (1) Design for testability for SoC based on scan chains: For each embedded circuit component, we will insert scan chains for improving testability. After that, referring to the suggested structure by IEEE P1500, the wrapper boundary cells and wrapper instruction register (WIR) will then be designed. We are targeting on reducing the width of WIR, the test application time, added circuit area, and power consumption during testing. (2) Design for test access mechanism (TAM) and wrapper sequential control (WSC): Based on the type of Daisy chain, TAM is designed with added decoder to make control for testing embedded circuits. We will target on making this part of design be reusable and in hierarchical form. (3) Employing the AMBA bus for parallel testing and design for testability: After generating test patterns and designing embedded circuits for testability, we will revise the circuits required for AMBA bus.

Project ID:PB9308-5077
External Project ID:NSC93-2220-E182-005