Low Voltage and Current Operation with High-Speed and Highly Nonvolatile Nanoscale Memory Devices for Next Generation of Mass Production

Nanoscale nonvolatile memory (NVM) devices with low voltage/current, high-speed writing and erasing of data, and highly compatible with CMOS technology are very interesting candidate in the semiconductor industry for the next generation of mass production. Those portable memory devices such as digital camera, video camera, mobile phones, personal digital assistance (PDA), iPOD, high quality notebooks, high-speed computers, etc. are using in our daily life. Floating gate nonvolatile devices are one of the memories which are using in those portable electronic goods. The floating gate memory devices can be scaling down to 32 nm technology node according to Intel’s announcement. Due to the huge requirements in the semiconductor market of the floating gate nonvolatite memory devices, the poly-Si-oxide-[silicon-nitride (Si3N4)]-oxide-Si (SONOS) charge trapping memory devices are also studied by several academics and companies. Macronix, Taiwan Manufacturing Semiconductor Company (TSMC), Samsung, South Korea, and etc are trying to produce as a huge scale of SONOS memory devices but they can produce a few, due to the limitation of understanding the Si3N4 material itself, retention issue and scaling problem. The SONOS has doubt to scale below 45 nm technology node. To overcome those problems in the SONOS charge trapping memory devices, we propose the new concepts of nonvolatile memory devices, i.e. Flash and CBRAM, for the new generation of mass production. In this work, we will focus on the high-k single layer or double layers nanocrystal quantum wells embedded in the high barrier height of high-k dielectrics with high work function metal gate. The high-k films will be deposited by sputtering/atomic layer deposition (ALD). The nanoscale MOSFET (chanel length (Lg): ＜100 nm) or FinFET (fin width (W): ＜10 nm) flash memory devices will be also fabricated. Finally, the NOR and NAND array circuits will be also designed and fabricated by using the high-k nanocrystals. To get better NAND performance, the metal nanocrystal array will be fabricated by using protein template in the metal/high-k/metal nanocrystal array/high-k/Si flash memory structure. The nanoscale MOSFET and FinFET flash memory devices with low voltage/current, high-speed and highly nonvolatile will be fabricated and could be realized. A new scheme of nonvolatile memory devices, CBRAM, with copper (Cu) or silver (Ag) nano-bridging in the high-k or chalcogenide materials will be designed and fabricated for the next generation of mass production. The CBRAM devices can be operated with extremely low voltage and current, high-speed of data writing and erasing, and highly nonvolatile. The nanoscale Flash, CBRAM devices and their circuits array will be fabricated for production. Our all approaches to realize and product using those new concepts of memory devices have been discussed point-wise below. Part 1: High-k nanocrystal quantum well flash memory devices and circuits 1. Design and investigation of high-k nanocrystal quantum well structure by sputtering/atomic layer deposition (ALD) system. 2. Adjustment of high-k Al2O3 tunneling oxide and high-k Al2O3 or HfAlO blocking oxide thickness with the capacitance equivalent thickness of ＜6 nm for 22 nm technology node applications. 3. Evaluation of memory characteristics of the flash memory capacitors 4. Tuning the high work function of metal gates such as platinum (Pt), nickel (Ni), tungsten (W) and iridium oxide (IrOx), etc, to reduce the back tunneling current from the gate electrode. 5. Design and fabrication of novel long and short channel length MOSFET memory devices with high-k nanocrystal quantum wells and IrO2 metal gate. 6. Design and fabrication of FinFET memory devices and the fin width is less than 100 nm. 7. Measurement and understanding the nanoscale flash memory device characteristics. 8. Design and fabrication of NOR and NAND flash memory array circuits using the high-k nanocrystal quantum wells. 9. Design and fabrication of memory circuits for production and joining with local semiconductor company, Taiwan, for production. 10. It can be used for very low voltage/current operation and super fast nanoscale flash memory devices. 11. Multi-level charge (MLC) storage and high-density applications. 12. It can be used for below 32 nm technology node. Part 2: Formation of metal nanocrystals array and flash memory devices 1. Novel metal nanocrystal array will be designed and realized by using protein template for 22 nm node NAND applications. 2. Investigation of size and distribution of metal nanocrystals by physical measurements. 3. Design and fabrication of novel metal nanocrystal flash memory capacitors with high-k tunneling and blocking oxide and high work function metal gate 4. Study of charging and discharging effects of metal nanocrystals by atomic force microscope (AFM). Memory characteristics of the single metal nanocrystal will be also investigated by AFM. 5. Metal nanocrystal array embedded in high-k dielectrics could have very small electrical thickness ＜6 nm. 6. Design and fabrication of MOSFET memory devices using single layer or double layers of metal nanocrystal array. 7. Measurement and understanding of memory characteristics in nanoscale flash memory devices. 8. Low voltage/current operation, high-speed and highly nonvolatile metal nanocrystal array MOSFET could be expected. 9. Design and fabrication of metal nanocrystal array FinFET memory devices. 10. Multi-level charge (MLC) storage with low voltage operation is expected. 11. Reproducible memory array could be realized. 12. It can be used below 32 nm technology node. Part 3: Conductive bridging random access memory (CBRAM) devices and circuits using chalcogenide and high-k based solid electrolytes 1. Design and fabrication of metal-insulator-metal (MIM) structure using novel high-k or chalcogenide based solid state electrolyte materials. 2. The Cu or Ag can be used as mobile ions in the high-k or chalcogenide based materials. 3. A noble metal of TiN or W as a bottom electrode can be used in the CBRAM device and this metal is very friendly with the CMOS technology. 4. Evaluation of solid electrolytes for CBRAM applications. 5. Realization of good memory devices with different annealing temperatures. 6. Thorough investigation of novel high-k and chalcogenide based materials. 7. Memory characteristics of solid electrolyte devices. 8. Design and fabrication of nanoscale CBRAM devices with via size less than 100 nm. 9. Uniformity study of good CBRAM devices with different solid state materials. 10. Measurement and understanding of nanoscale memory characteristics for array circuit applications. 11. Design and fabrication of array circuits 12. Realization of memory circuits for production and joining with local company, Taiwan. for production and marketing. 13. The CBRAM circuit could be realized with extremely low voltage as well as current, highly nonvolatile for 22 nm technology node. 14. It can be used for multi-level charge (MLC) storage applications 15. It is believed that continuous effort in our nonvolatile group will bring production for new generation of memory applications.

Project ID:PB9709-3569
External Project ID:NSC97-2221-E182-051-MY3