Mimo Coded Modulation Signal Design and Scheduling for the Iterative Detection Decoding Receiver

Low-density parity-check (LDPC) code has been selected as the error-control coding for the 5th generation mobile networks (5G), since that the high throughput decoding hardware can be implemented using the combination of LDPC codes and iterative belief propagation (BP) decoding algorithm. However, a high throughput communication cannot be achieved using only the fast decoder, high-order modulation and multiple-input multiple-output (MIMO) transceiver are also required. For the receiver, the operations of the MIMO interference cancellation, modulation symbol detection and code bit decoding must collaborate efficiently. In order to meet these criteria for high throughput communication, this multi-year project will invest in the combinational design including the constellation labeling of high-order modulation and LDPC code structure, the scheduling for the corresponding iterative detection and decoding (IDD) receiver, and the hardware implementation for the function verification. In the first year, the combination design for the high-order modulation labeling and code structure will be invested, in order to provide both low decoding threshold and low error floor performance. Considering the efficiency of the hardware implementation, QC-LDPC code will be selected for this coded modulation design. In the second year, the scheduling arrangement for the IDD algorithm will be investigate. The update order, or propagation path, that provides the most reliable detection and decoding messages will be identified, and be applied to the coded modulation designed in the previous year in order to accelerate the convergence of the iterative IDD operation. In the third year, the cancellation techniques for the MIMO detection will be included in the arrangement of scheduling, and the receiver will be implemented using FPGA. The limitation of the hardware circuit, such as the pipeline architecture and the memory access bandwidth, will be considered in the design criteria. During the project with total three years, the signal design and the IDD receiver scheduling for the MIMO coded modulation transceiver will be accomplished, along with the hardware implementation that meet the standard of high throughput for the 5G protocol.

Project ID:PB10608-2428
External Project ID:MOST106-2221-E182-010