Modeling and Analysis of Dopant Activation Affected by Reactions in the Preamorphized Layer

The use of nonplanar field effect transistors (FET) such as fin field effect transistors (FinFETs) has dominated the integrated circuit market. FinFETs use a small cross-sectional fin structure to suppress short channel effects. However, this causes a high series resistance, degrading the operation speed of integrated circuits. High dopant activation is needed to improve the performance of transistors. High-dose ion implantation amorphizes substrate surface and solid-phase epitaxial regrowth (SPER) during subsequent annealing would produce supersaturation of dopants, leading to high active concentration over the solid solubility of dopants. Previous studies have demonstrated dopant diffusion in the amorphous layer. However, the reactions between dopants in the amorphous layer are not well understood. If clustering of dopants occurs in the amorphous layer, such clusters would prohibit incorporation of dopants into lattice sites during SPER and the amount of supersaturated dopants would decrease. This project will study dopant reactions in the amorphous layer and its impact on dopant activation. We will design different temperature ramping profiles to trigger dopant reactions in the amorphous layer. Hall measurement will be performed after SPER to analyze dopant activation. The difference between the dose of active dopants and that during ion implantation represents the amount of dopants involving in reactions in the amorphous layer. Carbon co-implantation will also be preformed to realize the mechanism of dopant reacting with carbon in the amorphous layer. Dopant reaction models can be developed based on the reaction mechanism and the results from kinetic Monte-Carlo (KMC) simulation. Continuum equation models will be established and integrated with conventional process simulation platform. The results of this study will help us to understand the dopant reactions in the amorphous layer so that series resistance in transistors can be minimized for better circuit performance.

Project ID:PB10608-3647
External Project ID:MOST106-2221-E182-061