Multi-Core Scheduling Optimization with Considerations of Heterogeneous Hardware

In recent years, multi-core architecture is widely adopted in the designs of high-end servers, personal computers and embedded systems, due to its potential in resolving energy and thermal problems. To further improve the system performance, heterogeneous memory devices and computing units are integrated in many advanced multi-core platforms. Such trends have imposed great pressure on better and more support from the operating systems to jointly manage heterogeneous hardware for the system efficiency enhancement. When heterogeneous memory devices are included in a system, the fast local memory, such as Scratchpad Memory, is used to bridge the performance gap between computing cores and memory devices, and the global memory, such as DRAM, has to keep a large amount of data and application images. When heterogeneous computing units are further considered, system engineers have to provide not only the task scheduling algorithms but also the rules for the synchronization among heterogeneous computing units. Such observations motivate this project to investigate the advanced multi-core platforms for the designs of real-time systems. This proposal illustrates the research plan for two years. In the first year, the proposal aims to develop real-time task scheduling algorithms over multiple cores with different access latencies for different memory devices, in which the worst-case execution time of a task depends on its memory allocation. The goal is to develop a framework to jointly schedule tasks onto cores and allocate heterogeneous memory for the execution of the tasks. When real-time applications are considered, we have to meet the deadline constraints by properly using the given heterogeneous memory and computing cores, and the objective of the to-be-developed algorithm is different to all the related work. In the second year, the proposal further explores platforms with heterogeneous computing units, such as Digital Signal Processors (DSPs), Graphic Processing Units (GPUs) and Field-Programmable Gate Arrays (FPGAs). When such platforms are studied, the challenge is on how to reduce the idle time of each computing unit so as to improve the throughput of the entire system. We will explore the synchronization problem of tasks among heterogeneous computing units and evaluate the context-switch overheads of tasks between two different computing units. The expected protocol should be developed to favor the high-priority real-time tasks and to reduce the unnecessary idle time of each computing units, and an analysis scheme should be provided to test whether the timing requirement of each real-time task will be satisfied. Benchmarks and real-time applications will be included in the experiments to better reveal the insight into the real-time system designs on heterogeneous hardware. As most of the existing multi-core real-time scheduling algorithms assume that the execution time of each task is given and fixed and are not aware of the heterogeneous memory and computing units, we believe that the results of this project could derive useful techniques to enhance the performance of the heterogeneous systems. After a good framework of tasks scheduling and resource management is provided, the performance of real-time scheduling algorithms will be greatly benefit from the advanced hardware technology.

Project ID:PB10401-0236
External Project ID:MOST103-2218-E182-004-MY2