Multilayer Nanoscale Crosspoints Memory with Al2O3 Film for High-Density 3D Stacks (II)

This project was applied for three years. However, first phase is ongoing under contract no. NSC101-2221-E-182-061 [使用三氧化二鋁薄膜於高密度三維結構之多階奈米點記憶體(I)]. I am applying for second phase of the above project. This project is very useful. To fulfill all requirements from ITRS roadmap, novel low energy and high-density multilayer cross-points memory using high-κ Al2O3 film in an asymmetric novel Ir/Al2O3/W structure for 3D stacks has been proposed for the first time. The scaling of this resistive switching memory device can be up to 50×50 nm2 using our novel approach of ion etching method, without conventional electron beam lithography technique. It is known that the interconnection in the flash memory devices with many stack layers is a challenging task. Conventional Silicon-Through-Vias (TSV) method is using for 3D IC. However, TSV method is expensive. In this project, a Cu pillar for 3D stack interconnection of the resistive switching memory will be formed by external bias, which is also novel approach for 3D memory technology and low cost process also. The outcomes of our novel multilayer nanoscale cross-points memory for 3D stacks have been discussed point-wise below. First year: Part 1: Nanoscale Ir/Al2O3/W cross-points memory 1. Nanoscale via diameter of 50 nm formation by RIE and PVD. 2. The resistive switching memory characteristics with low P/E currents of 1-50 μA. 3. P/E endurance or read endurance: ＞1010 cycles 4. Data retention of nanoscale device: ＞106s at 85oC 5. Uniformity and reliability improvement 6. High speed operation with a small program/erase pulse width of ＜100 ns. 7. Fabrication of multilayer nanoscale cross-points memory Part 2: Cu pillar formation on different bottom electrodes 1. High current carrying Cu pillar investigation with different bottom electrodes (BE). 2. Interfaces study by electrical measurements and TEM observations. Interfaces of Ir/Cu and W/Cu under external bias will be investigated and improved by controlling external current and biases. 3. Cu pillar formation with a length of 2 μm AlOx for 3D stack integration. Second year: 1. Design and fabrication of multilayer nanoscale cross-points memory with 3D stacks. We can design up to 4-5 memory layers with 5x5 or 9×9 arrays. 2. Integration with Cu pillar on a transistor layout. 3. Read and P/E endurances: ＞1010 cycles 4. Data retention of the 3D stacks: ＞106s at 85oC 5. Reliability and uniformity testing 6. High speed operation: ＜100 ns. 7. Fabrication a portable 3D cross-points memory with 9x9 arrays.

Project ID:PB10301-0501
External Project ID:NSC102-2221-E182-057-MY2