Multileyer Nanoscale Cross-Points Memory with Al2o3 Film for High-Density 3d Stacks

In our daily life, we are using portable electronic goods such as digital camera, video camera, mobile phones, personal digital assistance (PDA), iPOD, portable high quality notebooks, high-speed computers and DVDs and so on. To use long time and high-speed operation with high-density, a low energy operation of memory devices is required. It is well known that the conventional floating gate memory is going to scaling limit up to 20 nm technology node. According to the Macronix, the poly-Si-oxide-[silicon-nitride (Si3N4)]-oxide-Si (SONOS) charge trapping memory devices is difficult to scale below 22 nm technology node. To overcome this scaling issue and to get high-performance nonvolatile memories, the resistive switching memories are developing by many companies like Macronix, Samsung, Sharp, NEC Corporation, Sony, Nanya, ST Microelectronics, CEA-LETI, Numonyx, MDM, Panasonic, HP, and so on. That’s why it is very interesting topic to obtain high-density with low energy operation beyond 10 nm technology node. To fulfill all requirements from ITRS roadmap, novel low energy and high-density multilayer cross-points memory using high-κ Al2O3 film in an asymmetric novel Ir/Al2O3/W structure for 3D stacks has been proposed for the first time. The scaling of this resistive switching memory device can be up to ~50 nm using our novel approach of ion etching method, without conventional electron beam lithography technique. It is known that the interconnection in the flash memory devices with many stack layers is a challenging task. Conventional Silicon-Through-Vias (TSV) method is using for 3D IC. However, TSV method is expensive. In this project, a Cu pillar for 3D stack interconnection of the resistive switching memory will be formed by external bias, which is also novel approach for 3D memory technology and low cost process also. The outcomes of our novel multilayer nanoscale cross-points memory for 3D stacks have been discussed point-wise below. First year: Part 1: Evaluation of novel Ir/Al2O3/W cross-points memory 1. Design and fabrication of the Ir/Al2O3/W cross-points memory. The high-κ Al2O3 film can be deposited by sputtering or atomic layer deposition (ALD). A single layer of 10x10 cross-points array will be fabricated. The bottom electrode (BE) W and top electrode (TE) Ir will be deposited by sputtering. 2. The resistive switching memory device could be operated under ±2V and programming/erasing (P/E) currents of 1-50 μA. 3. P/E endurance or read endurance: ＞107 cycles 4. Data retention: 85oC-150oC 5. Uniformity and reliability improvement 6. High speed with a small program/erase pulse width of ＜50 ns for low energy nonvolatile memory applications. Part 2: Cu pillar formation in W/Al2O3/Cu structure 1. Fabrication of the Cu/Al2O3/W structure. The thickness of Al2O3 film is about 2 μm and investigation of Cu pillar (filament) diameter. 2. Transmission electron microscope (TEM) images of the Cu/Al2O3/W structure for pillar investigation. 3. Thickness dependent and current compliance (CC) dependent Cu pillar diameter investigation. 4. High current carrying (~100 mA) Cu pillar formation for 3D integration. Second year: Part 1: Nanoscale Ir/Al2O3/W cross-points memory 1. Nanoscale via diameter of 50 nm formation. 2. The resistive switching memory characteristics with low P/E currents of 1-50 μA. 3. P/E endurance or read endurance: ＞1010 cycles 4. Data retention of nanoscale device: 85oC-150oC 5. Uniformity and reliability improvement testing 6. High speed operation with a small program/erase pulse width of ＜50 ns. 7. Repeatability testing 8. Fabrication of multilayer nanoscale cross-points memory Part 2: Cu pillar formation with different orientations of BE 1. High current carrying Cu pillar investigation with different orientations of the bottom electrodes (BE). 2. Interfaces study by electrical measurements and TEM observations. Interfaces of Ir/Cu and W/Cu under external bias will be investigated and improved by controlling external current and biases. 3. A very high current (1A) carrying Cu pillar formation with a length of 2 μm for 3D stack integration can be investigated. Third year: 1. Design and fabrication of multilayer nanoscale cross-points memory with 3D stacks. We can design up to 4-5 memory layers with 5x5 or 10x10 arrays. 2. Integration with Cu pillar on a commercial driving transistor layout. 3. Investigation of the resistive switching memory characteristics with different current compliances. 4. Read and P/E endurances: ＞1010 cycles 5. Data retention of the 3D stacks: 85oC 6. Reliability and uniformity testing 7. High speed operation testing: ＜50 ns. 8. Repeatability testing 9. Fabrication a portable 3D cross-points memory with 10x10 arrays.

Project ID:PB10108-2225
External Project ID:NSC101-2221-E182-061