Parasitic Extraction of the PCB Interconnect for 50GHz RF-Modules

Apparently, the device shrinkage of standard CMOS processes continues from 0.18μm to 35nm currently as well as to 20nm or less in the near future. Therefore, it promotes the operation frequency of RF frontend modules from several GHz’s to more than 50-GHz. However, due to the parasitic effects of frontend module packaging on the printed-circuit board (PCB), these effects induce the mismatch between simulation results and measurement data. Meanwhile, as long as RF frontend circuits can be implemented on PC board, it is first selection due to low cost of PCB processes. Thus, detailed investigation on the analysis of parasitic effects should be considered for frequency ranging from several to 50GHz or more. Based on previous study on the design and fabrication of RF fronted modules as well as the simulation and measurement of PCB interconnection, the purpose of this project is to setup a high-frequency (up to 50GHz) parametric extraction platform for RF modules on PCB. Using four-port network analysis to measure S-parameter data and to derive related impedance matrices for parasitic extraction, these measured values are verified by timedomain reflectometry (TDR) injected by pulse generator of less than 0.1 pico-second. As a result, TDR-based loop-back measurement for interconnect with active devices have proved to be cost-effective, easy to calibrate and use, and accurate enough for parasitic extraction. Finally, Results from these techniques as improved by previous researches and software tools will be promoted to more practicability and innovation.

Project ID:PB9709-3588
External Project ID:NSC97-2221-E182-056