Physical Design and Verification of Timing, Power, and Signal Integrity for SoC (III)

The designers must use several tools and design methodologies to meet timing constrains of SOC designs. The new challenge of developing these EDA tools appears in chip level, such as multiple supply voltages, hierarchical integration of multiple soft IPs, signal integrity and delay estimations. A primary focus is to decrease the loops of VLSI design flow in SOC designs by considering signal integrity and timing constrains during floor planning. Because SOC designs often use ultra deep sub-micro meter process, the reliability of power/ground buses play a significant role. Besides, the chip level clock tree synthesis is also important. The objective of our project is to provide a series of efficient and comprehensive tools to perform physical verifications for SOC. The keys of the research include (a) establish interconnect RLC model and coupled parameter model (b) establish 3D power/ground routing RLC mesh model (c) establish standard cell/ IP library and conductance/loading models (d) develop delay, crosstalk, IP drop estimator (e) study simultaneous buffer insertion, buffer selection and wire sizing algorithm (f) analyze and verify the results of our physical verification tools.

Project ID:PB9308-5078
External Project ID:NSC93-2220-E182-006