Power-Aware Pipelining for Streaming Applications Running on Multi-Core Processors

Most modern embedded or mobile devices support multimedia operations. These operations, e.g., VoIP, IPTV, UTM etc, can be considered as a streaming data computation. To satisfy performance requirements for these applications, the multi-core processor design has been proposed, and becomes a widely-applied trend in computer architecture. This is a three-year project. In the first year, we will study the characteristics of the streaming data computing, and learn how to improve its throughput by multi-core processors. Our concept is to consider the cores in a processor as the function units in a pipeline datapath. Then we will propose different pipelining parallelism models to partition a streaming-data program into several chunks, and map each chunk into each core. When the streaming data flow through processor cores, they can be executed in a high data rate. In addition, we propose a dynamic voltage scaling mechanism for a pipelined multi-core processor. We assume that there are two supplied voltage/frequency levels in a processor. When a core gets lightweight workloads, a power controller will supply lower voltage/frequency to that core such that the total power consumption can be reduced during program execution. In the second year, we will construct an experimental platform, and choose the video-surveillance streaming program as the application target. The platform will use multiple FPGA extension modules to simulate multiple cores in a micro-processor. The IP of these modules can be implemented by many existed hardware development kits. We also connect these modules to a PC-based controller, which responds to program loading, execution status control, and performance/power-consumption monitoring. For video-surveillance streaming example, we will focus on application of elder falling detection. In this application, multiple video-surveillance streams will go through the multi-core processor to perform pipelined image-processing. We use this example to proof the functionality and efficiency for the theoretical designs proposed in the first year. In the third year, we will focus on another example application -- UTM (Unified Threat Management), which requires more parallelism to perform heavy streaming operations. The major work is to analyze software architecture in an UTM program, then partition the tasks into pipe-stages, and finally implement a pipelining scheduling mechanism to perform each task in the proposed platform. The goal is to apply our theoretical designs to this example such that the data rate (throughput) can be speeded while the power consumption can be reduced. By realizing this project, the team crews can get solid experience in designing processor architecture, and also, they can study the importance of system-level power/performance evaluations.

Project ID:PB9709-1907
External Project ID:NSC97-2221-E182-031