Process and Device Simulation for Stacked Transistors in Three-Dimensional Integrated Circuits

The project will developed a process and d device simulation system for three-dimensional integrated circuits, based on thin film transistor technology. Two different device stacking strategies will be applied in the research. The first one is to directly stack devices using the same device fabrication processes. The other stacking strategy is using wafer bonding and through silicon via technology after device fabrication processes are completed for each wafer. In the first year of the project, the research will focus on process simulation. A platform will be built up for applying stress on substrates. Stress experiments will be performed to study the strain in three-dimensional integrated circuits. Then heat transfer during stacking processes will be simulated. Heat transfer and strain analysis will be integrated in the process simulation platform to analyze thermo-mechanical behaviors between stacked device layers. For the second year, device behaviors will be studied based on results from process simulation and experiments. Electrical properties of devices under mechanical stress will be analyzed. Device simulation of thin film transistor memories will be performed in conjunction with parasitic effects from nearby stacked devices. The heat and hot carriers in stacked devices will also be simulated for reliability properties. Device compact models for three-dimensional integrated circuits will be built up in the third year. The models will consider the impact of grain boundary on the threshold voltage of thin film transistors. The models will be extended for memory devices. Previous device simulation results about heat and stress will be included. Finally, statistical models considering grain boundary distribution will be established. This will integrate process and device simulation for the development three-dimensional integrated circuit technology.

Project ID:PB10207-1928
External Project ID:NSC102-2221-E182-059