Soft-Error-Tolerant Arithmetic Circuit Design and Chip Implementation

With the progress of CMOS process technology, the design complexity and the transistor density in SoC systems increase rapidly, whereas the power supply voltage also decreases rapidly. It leads to the Soft-Error Rate (SER) in SoC designs also increasing rapidly, the reliability in arithmetic circuits decreased as well. Therefore, the SET tolerant design becomes the major challenge in SoC designs in the future nano-scale era. In this project, we expect to develop the cost-efficient SET-tolerant arithmetic circuits design to enhance its soft-error immunity. We will also implement the proposed SET-tolerant arithmetic circuits through TSMC 40nm CMOS process to verify and demonstrate the ability in SET tolerance. In this way, the soft-error rate can be greatly reduced and the reliability of arithmetic circuits can be greatly enhanced, especially in the low supply voltage, small gate capacitance, and low signal-to-noise environments. Among them, our main design goal is to design an arithmetic circuit with higher soft error tolerant ability but sacrificing lower computation performance and lower hardware cost. In arithmetic circuits, we focus on the development of SET-adder/SET-multiplier designs, SET-FIR/SET-FFT, and SET-Motion Estimator/SET-Viterbi Decoder. Our design goal is to enhance the soft-error tolerance with lower hardware cost and lower performance degradation. In the SET-tolerant adder design, we proposed a modified C-element with lower speed penalty, which can save about half delay time. To adopt modified C-element in the modified carry merge tree, which combined ECD together with ECTO, we can not only lower the speed penalty in ECTO, but also save the area overhead in the ECD architecture. In the SET-tolerant multiplier design, we replace the conventional reduced-precision-replica by a weigthed- reduced-precision-replica to reduce the chip area and maintain the SER at the same time. We also proposed a multiplexer redundancy technique in MSB of main block to increase the SET immunity and enhance the computation accuracy of multiplier circuits. In the universal SET-arithmetic circuit architecture, we propose a time/space shared reduced-precision-replica design to lower the hardware cost. In the SET-FIR/FFT design, we apply Shift-and-Add architecture to replace the conventional multiplier/adder based architecture, which can greatly save hardware cost and greatly enhance soft error tolerance. In the SET-Motion Estimator/SET-Viterbi Decoder design, we remove the critical path in the original design to enhance the chance of using ECTO instead of ECD, which can achieve high soft error tolerance more hardware-efficient. In the first year, we will develop the SET-tolerant FIR and SET-tolerant FFT chip designs in TSMC 40nm CMOS process. In the second year, we will develop the SET-tolerant Motion Estimator and SET-tolerant Viterbi Decoder chip designs in TSMC 40nm CMOS process.

Project ID:PB10202-1053
External Project ID:NSC101-2628-E182-002-MY2