Soft-Error Tolerant Latch/Flip-Flop Circuit Design and Chip Implementation

With the progress of VLSI process technology, the design complexity and the transistor density in SoC systems increase rapidly, whereas the power supply voltage also decreases rapidly. It leads to the Soft-Error Rate (SER) in the SoC designs also increasing rapidly, especially in the latches. Therefore, in the near future nano-scale era, the SER tolerant design becomes the major design challenge in the SoC designs. In this project, we will develop some Single-Event-Upset tolerant (SEU-tolerant) techniques to enhance noise-immunity in VLSI digital latch circuits. We will implement the 32-bit ALU chip containing with SEU-tolerant latches through TSMC 90nm process. The SEU-tolerant ALU is expected to perform better SER immunity. For various SER applications, we develop 4 kinds of SEU-tolerant latch design. In the Isolated Schmitt-Trigger based SEU-tolerant latch design, we add one isolation mechanism to avoid voltage contention occurrence. In the Isolated DICE-based SEU-tolerant latch design, we add the isolation transistors to prevent output nodes from SEU interference. In the Split C-element based SEU-tolerant latch design, we not only split the SEU path but also enhance the feedback path to enhance SEU-tolerance. In the TPDICE based SEU-tolerant latch design, we enhance its clock signal control to lower the sacrifice in propagation delay. Through this project, we expect to develop the cost-efficient SEU-tolerant latch design to enhance the soft-error immunity in SoC chip design. By this way, the soft-error can be greatly reduced no matter in the latches/ flip-flops or SoC chips, especially in the low supply voltage, low gate capacitance, low Signal-to-Noise environments.

Project ID:PB10001-0997
External Project ID:NSC99-2221-E182-062-MY2