Project Details
Abstract
With the progress of CMOS process technology, the design complexity and the transistor density in
SoC systems increase rapidly, whereas the power supply voltage also decreases rapidly. It leads to the
Soft-Error Rate (SER) in SoC designs also increasing rapidly, the reliability in arithmetic circuits
decreased as well. Therefore, the SET/SEU tolerant design becomes the major challenge in SoC designs
in the nano-scale era. However, individual SEU-tolerant sequential circuit designs and SET-tolerant
arithmetic circuit designs cannot meet the requirement in a practical system because the soft-error
propagation chains are not broken and the overall soft-error tolerance would be greatly lowered. In this
project, we expect to develop SET/SEU-tolerant co-design to enhance the soft-error immunity in the
arithmetic circuits. We will also implement the proposed SET/SEU-tolerant arithmetic circuits through
TSMC 28nm CMOS process to verify and demonstrate the ability in SET/SEU tolerance.
In SEU-tolerant sequential circuit designs, we will develop a parallel conserve replica isolation
technique, a C-element with feedback protection in its fragile nodes, a dynamic feedback controlled
isolation mechanism, and a vector-ganged CLK protection technique in the SEU-isolated latch designs. In
this way, we can ensure SEU problems not been converted to SET-propagation problems. In SET-tolerant
arithmetic circuit/architecture designs, we develop an error-reshaping technique to overcome the
bottleneck of SET accumulation and SET induced SEU issues. Moreover, we expect to break through the
limitation of SET-tolerant arithmetic architecture cannot be adopted in feed-back DSP systems and
propose a unified SET/SEU tolerant design that can be applied into both feed-forward and feed-back DSP
systems. In this way, we can ensure SET errors not been acculturated as serious SEU problems. More
important, we go further to design the soft-error-tolerant mechanism for protecting the clock signal and
main control signals in system integration level. In this way, we can improvement SET-tolerance with
guaranteed signal quality, which can ensure the SET-tolerant ability still be preserved after circuit
integration. In the first year, we will develop the SET/SEU co-tolerant FIR/IIR chip designs in TSMC
28nm CMOS process. By adopting the inherent existing spatial/temporal redundancy to design the
SET-tolerant combinational circuits combined with SEU-tolerant sequential circuits with the parallel
conserve replica isolation technique and dynamic feedback controlled isolation mechanism, we can avoid
the SET/SEU chain effect by SET/SEU co-tolerant designs. In the second year, we will develop a unified
SET/SEU-tolerant FIR/IIR/FFT/ME chip designs that can support in both feed-forward and feed-back
DSP systems in TSMC 28nm CMOS process. With spatial/temporal redundancy sharing and
feed-forward/feed-back interleaving processing, we can widely extend the application field of SET/SEU
co-tolerant designs. Moreover, the blind spots on CLK/control signals can be removed in the proposed
SET/SEU-tolerant chip designs and the overall system soft-error immunity can be greatly enhanced.
Project IDs
Project ID:PB10608-3596
External Project ID:MOST106-2221-E182-069
External Project ID:MOST106-2221-E182-069
Status | Finished |
---|---|
Effective start/end date | 01/08/17 → 31/07/18 |
Keywords
- Soft-error-tolerant
- Soft-error-upset-tolerant
- Soft-error-transition-tolerant
- SEU/SET-tolerant
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