Study and Design of Fast Btc Decoding Algorithms and Parallel Decoding Circuits

Block turbo codes (BTCs) have been shown to offer performance close to the Shannon’s Limit. Besides, compared with convolutional turbo codes, BTCs have lower interleaving hardware complexity, lower decoding complexity and higher code rate. Due to that, BTCs have been adopted in many fields like IEEE 802.16 standard, satellite communication systems, and digital storage systems. However, the decoding process of BTC involves lots of the algebraic decodings such that the decoding latency is still long; therefore, BTCs are limited to apply in the real-time communication. In addition, the decoding algorithm of BTCs is irregular, which is hard to implement the BTC decoder in hardware. There are two goals in this proposal. The first is to develop a BTC decoding algorithm with different number of algebraic decodings for distinct rows (or columns), according to syndrome, reliability and soft output information to reduce the requirement of algebraic decodings and the decoding latency without performance loss. The second is to utilize the regularity of the decoding for majority-logic decodable codes to develop a parallel BTC decoding algorithm for the hardware implementation of the BTC decoders.

Project ID:PB10007-2294
External Project ID:NSC100-2221-E182-040