The Application of Graphene Resistive Switching Field Effect Transistor on 1T Nonvolatile Memory Array

Project: National Science and Technology CouncilNational Science and Technology Council Academic Grants

Project Details


The two-dimensional graphene sheet, combined with the concept of resistive random access memory (RRAM), is studied in this project. The resistive switching (RS) operation will induce the capacitance change, leading to the Dirac voltage shift of the graphene field effect transistor (GFET) for memory application. The different RS will be operated with n-type and p-type graphene to achieve the graphene memory and the multilevel cell (MLC) operation will be used to realize the high-density requirement. Then, the 1T graphene RS memory with 33 array prototype will be finished. The project can be divided into three parts: 1. Unipolar and bipolar RS graphene memories with graphene bottom electrode (BE) will be developed. For unipolar, the doping of graphene and the charges within the RS layers will be modified to achieve the different polarities of resistive switching and read operation. For bipolar, the RS materials will be modified to change the voltage of resistive switching and read operation. The resistive switching voltage should be larger than the read voltage to avoid the read disturbance. 2. A MLC-operated graphene RS memory with graphene bottom electrode (BE) will be developed to realize the high-density application. The 2-bit MLC operation graphene RS memory will be fabricated and the distribution of the resistance and Dirac voltage shift will be discussed. Then, the MLC-operated memory characteristics and device reliability will be analyzed. 3. A 1T graphene RS memory with 33 array prototype will be developed. The masks will be designed to fabricate the graphene memory array and the process will be optimized to achieve the fabrication of memory array prototype. The RS operation of memory array to change the Dirac voltage will be realized and the operation disturbance will be discussed for the development of high-density memory array architecture.

Project IDs

Project ID:PB10401-1775
External Project ID:MOST103-2221-E182-061-MY3
Effective start/end date01/08/1531/07/16


  • graphene
  • RRAM
  • multilevel
  • Dirac point
  • array


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