The Effect of Tsv Implementation on Device Electrical Performance, Die Strength, and Thermal-Mechanical Properties and Heat Dissipation of Its 3-D Die Stacking Packages

The technology evolution of integrated circuit (IC) semiconductor industry has two trends: miniaturization (more Moore) and diversification (more than Moore). Unlike the system on chip (SOC), the diversification (or heterogeneous chip integration) without scarifying electrical performance has gained more attention, due to its cost effectiveness, feasibility, and compatibility to current manufacturing infrastructures. To realize this diversification, through-silicon-via (TSV) interconnect technology plays an important role of integrating multi-chips in three-dimensional (3-D) manners together as a system or sub-system. However, the TSV technology has several issues to be resolved before implemented in the 3-D IC integration. The issues include the degradation of electrical performance (mobility) of transistors and strength of the chip dies induced by TSV thermal stresses, the heat dissipation problem due to 3-D stacked chip in packages, thermo-mechanical problem in package and module levels and so on. Currently, world-wide semiconductor industry, research institution and academia have put a lot of efforts and resources in attempt to address these fundamental issues related to 3-D IC integration with TSV technology. The objectives of this study are to investigate the effect of TSV structures in silicon chips on thermal stress, electrical properties and chip strength, and to further study the heat dissipation and thermo-mechanical behaviors of TSV chip-stacked packages and modules. The methodologies used includes experimental methods—Twyman-Green interferometry, moiré interferometry, newly-developed die strength test, and interfacial adhesion test, numerical methods—Ansys and CFdesign (finite element simulators), and related theories—Stoney equation, Timoshenko bi-material, plate-on-elastic-foundation theory, stress-electrical mobility relationship and some heat transfer fundamentals. Phase I (in the first year) will focus on the TSV geometry- and process-parameter effects on the thermal residual stress, electrical mobility of surrounding transistors and strength of silicon chips. The test samples and process conditions will be supported and offered by local memory and logic semiconductor foundries. Phase II (in the second year) will aim to study the heat dissipation and thermal stresses of TSV chip-stacked packages and modules, which will be fabricated and assembled by both local semiconductor foundry and packaging house. As a result, the project will eventually create a close collaboration with local semiconductor companies and further help them to tackle these pretty hot issues which the world-wide semiconductor companies and academia are currently facing. And it is hopeful that this search collaboration will show a good example and success of partnership between academia and industry.

Project ID:PB10107-1739
External Project ID:NSC101-2221-E182-024