The Process Development for Smart-Cut Silicon-On-Insulator by Two-Step Annealing of Plasma Immersion Ion Implantation

  • Lai, Chao-Sung (PI)

Project: National Science and Technology CouncilNational Science and Technology Council Academic Grants

Project Details

Abstract

Silicon-on-Insulator (SOI) device can improve the isolation, suppress the short channel effect and leakage current. Therefore, much attention was on the SOI devices. Use of fully depleted SOI substrates provides advantages such as reduced junction capacitance, immunity to radiation and latch-up, and improved performance over bulk Si devices. The traditional ion-beam line SOI processes, including SIMOX or Ion-Cut, are time consumption and high cost, especially for the large area wafers. PIII can totally eliminate this problem except the SOI uniformity, because that it is difficult to implant with selective ions. This causes serious issue of SOI uniformity and affects the device electrical characteristics. In this project, we propose three processes and measurement methods to improve SOI film quality. (1) Part I - Surface Roughness Improvements by Pre-Implant Induced Hydrogen Gathering: Diffusion and gathering of hydrogen are dependent on the location of crystal damage. We could obtain sharper hydrogen distribution by pre-implant ions (e.g. Si, Ge, Ar, et al. ) before hydrogen PIII process, and then improve the film uniformity. (2) Part II - Two-Step Annealing Ion-Cut SOI: After PIII, the temperature and time of two-step annealing affect the distribution of hydrogen and film uniformity. We divide RTA process into two steps: temperature range of step 1 is 100~200oC, hydrogen could get sufficient time to diffuse and not to separate. Temperature of step 2 is 400~600oC for the ion-cut process. This two-step RTA process is expected to improve the SOI film uniformity. (3) Part III - Electrical Characterization of PIII SOI Devices: SOI wafers will be measured electrically by various structures. In order to understand and estimate the quality of SOI films, electrical analyses by the following methods are employed: a. Electrical Direct Contact Method b. Virtual Short Method c. Pseudo-SOI MOSFET Method

Project IDs

Project ID:PB9605-0228
External Project ID:NSC96-2623-7182-001-NU
StatusFinished
Effective start/end date01/01/0731/12/07

Keywords

  • SOI
  • PIII
  • Two-step annealing

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