The Study of a Source Synchronous Link with Wide Range and Multi-Phase Dll

One of I/O system, system-synchronous had been announced for many years. A clock generator provides clock for both the transmitting and receiving party. Those years most clock delays are being ignored in the system. They are so small compared to the available clock period. But as speeds increased, managing clock delays became more difficult, then impossible. One way to improve the problem was to send a copy of the clock along with the data. This method is called Forward clock (or source-synchronous link). In source-synchronous links, the transmitter transmits its clock on a separate channel along with multiple data channels. The receiver uses forwarded clock as a frequency reference. However, at high data-rates, clock skew can be a significant increase the bit-error rate (BER) and thus these links need to perform skew compensation to ensure that data is optimal sampled. The receivers also need to produce multiple phase-shifted clocks to sample the interleaved data. An optional PLL or DLL receives the forwarded clock and performs deskew or jitter-filtering output signal. This project proposed a multi-phase and wide range DLL to solve the skew problem in the forward clock system. We propose a new architecture with all-digital DLL. Beside this, a new wide range digital-controlled delay line with 4 phases of the output clock is proposed. The proposed DLL circuit can acquire the phase of a clock signal from 1 MHz frequency to 2 GHz frequency. The frequency range ratio reaches 2000 times. This project is going to design with 0.18μm process technology. The estimated performance of this project with power consumption is less than 10mW and phase error is less than ±10ps.

Project ID:PB10608-3593
External Project ID:MOST106-2221-E182-067