The Study of Energy-Aware Task Scheduling Algorithms for Multi-Core Real-Time Systems

Modern IC design techniques and wireless network techniques drive explosive developments on the embedded computing, personal computing, and pervasive computing etc. Many related products, e.g., smart phone, game boxes, are also proposed in an amazing time-to-market speed. The common characteristics of these products are small-size, high-performance, within real-time computations. To satisfy the expected quality-of-service, these products start to use the multi-core processors in their architecture. The issues of power consumption or thermal reduction on a multi-core processor, however, are very challengeable than ever before. Most previous studies have proposed the task scheduling algorithms with the dynamic voltage scaling technique to reduce a multi-core processor’s power consumption while satisfy the real-time requirements. Most of them, however, focused on periodic task scheduling, which belong to the studies of static task scheduling, or ignored the side-effects of voltage transition overheads when performed the DVS scheduling. In this project, we focus our research on designing the run-time aperiodic task scheduling algorithms for multi-core real-time systems. We first model the task scheduling problem as an Integer Linear Programming (ILP) problem, and use the ILP solver to find the optimal scheduling results, given a set of architectural models. These optimal scheduling results can be considered as an ideal case of the task scheduling. Considering the time complexity of finding the optimal results, we design another heuristic task scheduling algorithms to find the approximation solutions. In our study, we also consider the voltage transition overheads which include the voltage transition energy and transition time when the system uses multiple supply voltages to perform task execution. In this one-year project, we will implement an experimental simulation platform to simulate a multi-core real-time system with a multi-voltage DVS module. In this platform, we will also generate different task sets of different workloads for integrated evaluation. By realizing this project, we expect that all members which join this project can learn much knowledge and experiences on designing low-power multi-core processors.

Project ID:PB10007-2315
External Project ID:NSC100-2221-E182-052