The Study on Low Hole Effective Mass P-Type Metal Oxide Materials and Thin Film Transistor Devicefabrication (II)

  • Liu, Kou-Chen (PI)

Project: National Science and Technology CouncilNational Science and Technology Council Academic Grants

Project Details

Abstract

Recently, stannous-oxide/tin-monoxide (SnO) was demonstrated to exhibit promising ^-type characteristics that are suitable for a ^-channel TFT. This material can possess a relatively high hole-mobility as its valence band maxima (VBM) consisted of spatially spread Sn 5s2 cations hybridized with fully occupied 2p orbitals that allows direct overlaps between neighbouring cations leading to a higher dispersion of valence band and a lower hole effective mass. Nevertheless, implementation of this material to fabricate thin-film complementary metal—oxide—semiconductor (CMOS) devices comprising both p- and ^-type TFTs is still limited in the literature, meanwhile such CMOS inverters are the basic building blocks for complex integrated circuits for system-on-chip and other electronic applications. In our last first year project, we have explored the recipes for fabrication of stable p-type SnO thin films by sputtering method, accompanied by first principle material simulations. We found that the annealing process is the main recipe to fabricate a stable p-type . In this second year project, we propose systematic study for fabricating -based CMOS through single-step channel-deposition via industrial compatible sputtering and/or ion-assisted beam techniques followed by oxygen plasma treatment (OPT). The simple-step procedure can be achieved by controlling the concentration of oxygen on the top of gate dielectrics by varying the plasma powers during the OPT on the as-deposited oxide layer. This oxygen addition will act as the ambient-contact for the SnO during the annealing process. The semiconducting tin-oxide layer, whether it is p-type or 万-type, is constructed by letting the residual oxygen to react with the layer upon an annealing process conducted at the end of the deposition. Thus, the channel can be produced only one-step of deposition. Therefore, a practical CMOS inverter can be produced using a rather simple scheme. Three scenarios of CMOS preparation are given in this proposal. For a higher performance CMOS, the hybrid p-type SnO and 万-type IGZO CMOS fabrication are also proposed. These proposed investigations are supported by both theoretical simulation and experimental approaches, so that a detailed and comprehensive understanding to achieve and improve the desired results can be fulfilled

Project IDs

Project ID:PB10408-5762
External Project ID:MOST104-2221-E182-031
StatusFinished
Effective start/end date01/08/1531/07/16

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