Thermal Stress and Deformation of Cu-Tsv Chip Package during the Stacking and Molding Processes : Measurement and Simulation

The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260℃, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moire is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moire have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.

Project ID:PB10307-1149
External Project ID:MOST103-2221-E182-024