Variation-Aware Near-Threshold-Voltage Sustainable Cerebral Recycled Energy SoC Design( I )

In the Sustainable CErebral Recycled Energy SoC Platform (CERES) research project, this sub-project plays a key role in energy/power saving and enhancing energy/power efficiency. To overcome the power-saving challenge, which is the most critical bottleneck in Moore’s Law, we would develop the near-threshold-voltage (NTV) technique to allow the SoC system operating in a lower operating voltage to enhance the power efficiency. The NTV technique is vigorously promoted by Intel from 2012 and NTV is the operation region that a SoC chip can gain the highest power efficiency. NTV brings the benefits of improving the efficiency of energy use, but it also gives rise to some serious design challenges. In this sub-project, we will develop some key techniques to enhance the PVT variation tolerance, enhance the noise-tolerance ability, and compensate the performance degradation in a super-linear way in the NTV environment: In PVT variation tolerance enhancement: We would develop the VT balancer technique that can tolerate global chip variation, the adaptive and latency variable ReVIVaL technique that can tolerate PVT variation and clock overlapping, which both can help enhance the PTV tolerance in NTV environment. Besides PVT variation, we also develop a Relaxed-DSP architecture that can relax the carry propagation path between MSB and LSB, which can balance the distribution of signal propagation path to provide an inherent computation delay variation tolerant environment. To let the CERES chip can self-adjust to tolerate PVT variation adaptively; we design a path-balancing asynchronous active-warning technique to tolerate both PTV global and local variations in a much safer and energy-efficient way as compared with the synchronous systems. In Noise-Tolerance Enhancement: In combinational circuits, we develop a single rail mixed temporal/spatial redundancy probabilistic-based noise-tolerant technique to resist noise interference under NTV environment, which can save more than half chip area, more than half PDP overhead, and maintain the same noise-tolerance. In the sequential circuits, we develop a cross-latching C-element mechanism combined with non-linear critical charge protection mechanism to provide an area-efficient and energy-efficient robust soft-error-upset tolerant latch design, which can survive well under NTV noisy environment. In Compensation for NTV Performance Degradation: We would develop a carry-relaxed bit-serial/column-parallel technique to shorten the critical signal propagation path and balance the path delay, which can help minimize the signal propagation delay difference in NTV environment to provide a big chance for super-linear performance degradation compensation. Finally, we develop a main-DSP-gated reduced-precision-replica (RPR) only voltage-over-scaling architecture, which let the high-speed, ultra-low-voltage fit RPR replaces the main-DSP, co-working with the relaxed-DSP architecture. In this way, we can achieve a super-linear performance compensation for NTV system, where its performance compensation efficiency is much higher than parallel and pipeline solutions do.

Project ID:PB10305-0549
External Project ID:MOST103-2220-E182-001