一種半導體互聯線及其在積體電路製程之後的製造方法\

Cher-Ming Tan; Chao-Sung Lai; UDIT NARULA

一種半導體互聯線及其在積體電路製程之後的製造方法\

Translated title of the contribution: THE SEMICONDUCTOR INTERCONNECTION LINE AND MANUFACTURING METHOD THEREOF

Cher-Ming Tan (Inventor), Chao-Sung Lai (Inventor), UDIT NARULA (Inventor)

Department of Electronic Engineering

Research output: Patent

Abstract

The invention provides that the semiconductor interconnection line and manufacturing method thereof, in which including semiconductor substrate, dielectric layer, barrier metal, a-C layer, and metal layer.

Translated title of the contribution	THE SEMICONDUCTOR INTERCONNECTION LINE AND MANUFACTURING METHOD THEREOF
Original language	Chinese (Traditional)
IPC	H01L-023/532(2006.01);H01L-021/768(2006.01)
State	Published - 16 09 2017

Bibliographical note

公開公告號: 2.01733071E8
Announcement ID: 2.01733071E8

Cite this

@misc{97c420c48e644d088f2e4531e3d5f036,

title = "一種半導體互聯線及其在積體電路製程之後的製造方法\",

abstract = "本發明提供一種半導體互聯線(semiconductor interconnection line)之結構及其製造方法，而半導體互聯線結構包含半導體基板層，介電層(dielectric layer)，屏障金屬層(barrier metal)，石墨烯層，以及金屬層。",

author = "Cher-Ming Tan and Chao-Sung Lai and UDIT NARULA",

note = "H01L-023/532(2006.01);H01L-021/768(2006.01)",

year = "2017",

month = sep,

day = "16",

language = "繁體中文",

type = "Patent",

}

TY - PAT

T1 - 一種半導體互聯線及其在積體電路製程之後的製造方法\

AU - Tan, Cher-Ming

AU - Lai, Chao-Sung

AU - NARULA, UDIT

N1 - 公開公告號: 2.01733071E8 Announcement ID: 2.01733071E8

PY - 2017/9/16

Y1 - 2017/9/16

N2 - 本發明提供一種半導體互聯線(semiconductor interconnection line)之結構及其製造方法，而半導體互聯線結構包含半導體基板層，介電層(dielectric layer)，屏障金屬層(barrier metal)，石墨烯層，以及金屬層。

AB - 本發明提供一種半導體互聯線(semiconductor interconnection line)之結構及其製造方法，而半導體互聯線結構包含半導體基板層，介電層(dielectric layer)，屏障金屬層(barrier metal)，石墨烯層，以及金屬層。

M3 - 專利

ER -

一種半導體互聯線及其在積體電路製程之後的製造方法\

Abstract

Bibliographical note

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Cite this