Abstract
A method and apparatus for model-order reduction of general RLC interconnects in high-speed VLSI is disclosed. It has been known that reduced-order models can be yielded using the congruence transformation, which contains information of circuit moments of both circuit network and its corresponding adjoint network. By exploring symmetric properties of the modified nodal analysis formulation, the method needs only half of the system moment information compared with the previous ones. Passivity of the reduced-order model is still preserved.
| Translated title of the contribution | A method and apparatus for model-order reduction of general RLC interconnects in high-speed VLSI |
|---|---|
| Original language | Chinese (Traditional) |
| Patent number | I252996 |
| IPC | G06F 17/50(2006.01) |
| State | Published - 11 04 2006 |
Bibliographical note
公開公告號: I252996Announcement ID: I252996
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