一種超大型積體電路中同步電路時刻偏移量排程與最佳化設計的方法

Disclosed are a clock skew scheduling of a synchronous circuit in VLSI and an optimal design method which perform optimal process on the clock skew of a digital synchronous VLSI system and formulates the problem of optimizing clock skew as a quadratic equation. To evaluate reliability, a cost function of a quadratic equation is utilized to analyze an error between an ideal value of the clock skew and a feasible solution. During the calculation, several algorithms are utilized to speed up calculation and lower complexity. Finally, an ISCAS' 89 circuit is utilized as a test circuit, and the method of the present invention makes the clock skew in the circuit as close to a target value as possible according to a simulation result. As the clock of a circuit can provides an accurate operation time, an increase in reliability and efficiency of the circuit can be expected.