以主運算冗餘為基礎之低硬體成本、高抗軟錯誤能力算術電路晶片設計

Translated title of the contribution: Hardware-Efficient, High-Soft-Error-Tolerant Arithmetic Circuit Design based on Most-Significant-Part Main-Block Redundancy

藍珮純

Research output: Types of Thesis › Master's thesis

Translated title of the contributionHardware-Efficient, High-Soft-Error-Tolerant Arithmetic Circuit Design based on Most-Significant-Part Main-Block Redundancy
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2011
Externally publishedYes

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