以高精準固定寬度乘法器為基礎之低面積以及低功率的演算法層級抗雜訊架構

Translated title of the contribution: Area-Efficient Low-Power Algorithmic Noise-Tolerant Architecture Based on High-Accuracy Fixed-Width Multiplier
  • 莊尚默

Research output: Types of Thesis › Master's thesis

Translated title of the contributionArea-Efficient Low-Power Algorithmic Noise-Tolerant Architecture Based on High-Accuracy Fixed-Width Multiplier
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2011
Externally publishedYes

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