估測超大型積體電路中訊號延遲之方法

The invention is a kind of method for estimating signal delay in the VLSI circuit. The simplified model is structured with standard parasitic file of interconnected circuit, signal in-transition time, logic library and circuit structure by verilog description to calculate the node bias differences and branch current differences. The model can be maintained under passivity and stability. The operation mode of I/O nodes is accorded with the original system. Finally, using the signal time-domain simulation combined with equivalent capacitor, the cell delay of logic gates, wire delay of interconnect lines and wire transition of output signal can be calculated and analyzed.