低延遲變異之近臨界電壓CMOS電路分析與設計

Translated title of the contribution: Design and Analysis of near threshold voltage CMOS circuits with low delay variance

陳永勝

Research output: Types of Thesis › Master's thesis

Translated title of the contributionDesign and Analysis of near threshold voltage CMOS circuits with low delay variance
Original languageChinese (Traditional)
Supervisors/Advisors
  • Wey, I-Chyn, Supervisor
StatePublished - 2014
Externally publishedYes

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