低延遲SOVA渦輪碼解碼器之電路架構

Translated title of the contribution: A Low-Latency hardware Architecture for SOVA-based Turbo Decoder

張竣智

Research output: Types of Thesis › Master's thesis

Translated title of the contributionA Low-Latency hardware Architecture for SOVA-based Turbo Decoder
Original languageChinese (Traditional)
Supervisors/Advisors
  • Lu, Erl-Huei, Supervisor
  • Lee, J. Yen, Supervisor
StatePublished - 2003
Externally publishedYes

Access to Document

Cite this