低耗能超大型積體電路可測性設計之掃描鍊重序方法

A method and apparatus for reordering a scan chain so that the given constraints are met and the peak power consumption is minimized, is disclosed. The constraints include (1) maximum peak power consumption; (2) maximum scan chain length; (3) maximum distance between two successive registers. The developed tool can be embedded into the existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics are quickly judging if the problem has corresponding feasible solutions and searching the optimal solution. Given the scan chain declaration data and the scan pattern data, the modified ones, which satisfy the constraints, can be obtained.