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低耗能超大型積體電路可測性設計之掃描鍊重序方法
Translated title of the contribution
:
METHOD AND APPARATUS FOR SCAN CHAIN REORDERING IN LOW-POWER VLSI DFT DESIGNS
Wu-Shiung Feng (Inventor)
, Chia-Chi Chu (Inventor)
, CHIAMING HO (Inventor)
, HERNG-JER LEE (Inventor)
Department of Electronic Engineering
Department of Electrical Engineering
Research output
:
Patent
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Computer Science
Design
100%
Scan Chain
100%
Density Functional Theory
100%
Power Consumption
50%
Feasible Solution
25%
Engineering
Dft
100%
Maximum Distance
33%
Physics
Distance
100%