| Translated title of the contribution | Design and Implementation of a DSTATCOM with Modular Cascaded Multilevel Inverter for Load Compensation |
|---|---|
| Original language | Chinese (Traditional) |
| Supervisors/Advisors |
|
| State | Published - 2006 |
| Externally published | Yes |
使用模組化串疊式多階換流器設計與實現具負載補償功能之配電型靜態補償器
陳政達
Research output: Types of Thesis › Master's thesis